1. Field of the Invention
This invention relates to a pattern evaluation method and evaluation apparatus which evaluate a mask pattern formed on an exposure mask. Further, this invention relates to a pattern evaluation program which causes a computer to evaluate a mask pattern. In addition, this invention relates to a manufacturing method of a semiconductor device for forming a pattern on a semiconductor substrate by use of a mask which is determined to be an acceptable product by the above evaluation method or apparatus.
2. Description of the Related Art
In a process of manufacturing large-scale integrated circuits (LSIs), a method for transferring a pattern formed on an exposure mask to a wafer by use of the photolithography technique is generally used. With recent developments in the pattern miniaturizing process, the wavelength used for transfer has become almost equal to the pattern line width and the degree of difficulty in forming a desired pattern on a wafer is rapidly increasing. In order to cope with this problem, in the photolithography, the light phase effect is utilized or the optical proximity effect correction (OPC) method which corrects a variation in a transfer pattern caused by an influence of a proximity pattern is used.
Miniaturization of the pattern and increased complexity of the pattern due to the optical proximity effect correction increases an influence exerted by the mask pattern on a pattern formed on the wafer via the photolithography. For example, it becomes impossible to neglect a dimensional difference between the line width of the mask pattern and a desired value and a minute difference in the mask pattern caused by an error in the manufacturing process. Further, a large number of fine step differences are formed on the pattern by the optical proximity effect correction method and the area of a portion with a simple linear form becomes less. Therefore, conventionally, it becomes difficult to measure and manage the line width.
Based on the above condition, a method for evaluating a mask pattern by performing the lithography/simulation process is proposed (W. C. Wang et al. “Mask pattern fidelity quantification method” SPIE Vol. 5256 (2003) pp. 266 to 275). In the above method, an image of a mask pattern actually formed is acquired by use of a scanning secondary electron microscope (SEM) and a pattern contour is extracted from the image. Then, the lithography/simulation process is performed based on the pattern contour to evaluate the mask pattern according to whether or not desired lithography tolerance is obtained or whether or not a predictable wafer pattern has a form within a preset range.
However, the following problem occurs in the above type of method. That is, when the mask pattern is evaluated, a pattern contour is extracted from the image of the mask pattern and then the lithography/simulation process is performed based on the pattern contour to acquire predicted wafer pattern data. At the same time, desired wafer pattern data is acquired based on design data. Then, it is necessary to compare the above data items. At this time, it is difficult to align the predicted wafer pattern with the desired wafer pattern and it becomes impossible to precisely compare the predicted wafer pattern with the desired wafer pattern. As a result, there occurs a problem that the precision of the pattern evaluation process is lowered.